From fnaumann@mail.cs.uni-magdeburg.de Thu Jul 8 08:45:34 2004 Subject: Re: [MiNT] Trans.: Re: Questions about 68040 From: Petr Stehlik To: mint@lists.fishpool.fi In-Reply-To: <1089262936.40ecd558ec19f@imp6-q.free.fr> References: <1089262936.40ecd558ec19f@imp6-q.free.fr> Content-Type: text/plain; charset=iso-8859-2 Message-Id: <1089268664.2096.6.camel@joy.home> Mime-Version: 1.0 X-Mailer: Ximian Evolution 1.4.6 Date: Thu, 08 Jul 2004 08:37:45 +0200 X-MIME-Autoconverted: from 8bit to quoted-printable by ns1.avonet.cz id IAA28306 X-Virus-Scanned: by amavisd-new-20030616-p7 (Debian) at fishpool.fi Delivered-To: mint@lists.fishpool.fi X-ecartis-version: Ecartis v1.0.0 Sender: mint-bounce@lists.fishpool.fi Errors-to: mint-bounce@lists.fishpool.fi X-original-sender: joy@sophics.cz Precedence: bulk List-help: List-unsubscribe: List-ID: X-List-ID: X-Milter: ClamAV 0.70/0.70kjel X-Milter: milter-regex 1.5jel X-Milter: ClamAV 0.70/0.70kjel X-Milter: milter-regex 1.5jel Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by prinz.cs.uni-magdeburg.de id i686jGCj001910 V Čt, 08. 07. 2004 v 07:02, Xavier Joubert píše: > This is impossible on 68 040 and 68 060 ! These CPUs cannot simulate a read or > write access. They always restart an access on an RTE. This is a major > differemnce between 68 030 and 68 0[46]0. this is what I tried to warn about earlier but didn't remember the facts :) > When you encounter a bus fault for reading of 0x5a0, tweak PMMU to allow for > reading (and reading only) of 0x0-0x1000 (or 0x0-0x2000, I don't which page > size MiNT uses), modify SR on stack to set TRACE mode, and install tour own > trace handler. Then ReTurn from Exception. Or if you don't let it read the address (say if it's a hardware reg) but you want to supply your own value to the right register you basically have to write a 68040 emulator. Petr